文章目录前言1.创建Vivado工程2.创建axi4_rw_testIP核。3.创建axi4_rw_testIP核4.添加tb文件5.开始仿真6.搭建bd文件7.创建vitis工程并编写代码总结前言本文仅作个人学习记录不具有参考价值。以下操作均基于 hello world 实验工程进行修改读者需提前准备好可正常运行的 hello world 工程作为基础。1.创建Vivado工程在 hello world 工程的基础上打开 Vivado 并加载已有工程进入 Block Design 设计界面。2.创建axi4_rw_testIP核。在 IP Catalog 中搜索并创建名为 axi4_rw_test 的 AXI 主机 IP 核。创建过程中需根据向导提示配置 AXI 接口参数包括地址宽度、数据宽度、突发长度等保持默认配置即可。创建完成后该 IP 核会自动添加到当前工程的 IP 库中并可在 Block Design 中通过 Add IP 的方式将其添加到设计中用于后续对 DDR 进行读写测试。3.创建axi4_rw_testIP核在 IP Catalog 中搜索并创建名为 axi4_rw_test 的 AXI 主机 IP 核。创建过程中需根据向导提示配置 AXI 接口参数包括地址宽度、数据宽度、突发长度等保持默认配置即可。创建完成后该 IP 核会自动添加到当前工程的 IP 库中并可在 Block Design 中通过 Add IP 的方式将其添加到设计中用于后续对 DDR 进行读写测试。打开 axi4_slave_v1_0_S_AXI.v 文件位于 D:\ldy\VivadoProjects\VIvado2020.3\ATK\Navigator7020\pl_rw_ddr\ip_repo\axi4_slave_1.0\hdl 目录下对该从机 IP 核的 Verilog 源码进行两处关键修改找到always(mem_data_out, axi_rvalid)语句将其替换为always(*)。这样修改的目的是让组合逻辑块对所有的输入信号变化都敏感避免因敏感列表不完整而导致仿真时出现信号更新不及时的问题确保读数据通道在仿真中能正确响应地址变化。找到localparam integer OPT_MEM_ADDR_BITS 7;语句将其替换为localparam integer OPT_MEM_ADDR_BITS 12;。该参数定义了从机内部存储器的地址位宽修改后从机的存储空间由原来的 128 字节扩展到 4096 字节从而能够覆盖主机在测试中访问的整个地址范围保证读写测试的完整性。4.添加tb文件在D:\ldy\VivadoProjects\VIvado2020.3\ATK\Navigator7020\pl_rw_ddr\pl_rw_ddr.sim\tb中创建tb_axi4_rw_test_v1_0_M_AXI.v//****************************************Copyright (c)***********************************////原子哥在线教学平台www.yuanzige.com//技术支持http://www.openedv.com/forum.php//淘宝店铺https://zhengdianyuanzi.tmall.com//关注微信公众平台微信号正点原子免费获取ZYNQ FPGA STM32 LINUX资料。//版权所有盗版必究。//Copyright(C) 正点原子 2023-2033//All rights reserved//----------------------------------------------------------------------------------------// File name: tb_flow_led// Created by: 正点原子// Created date: 2023年1月31日11:12:36// Version: V1.0// Descriptions: LED灯闪烁激励文件////----------------------------------------------------------------------------------------//****************************************************************************************//timescale1ns/1ns//仿真单位/仿真精度moduletb_axi4_rw_test_v1_0_M_AXI();//parameter defineparameter CLK_PERIOD20;//时钟周期 20nsparameter C_M_AXI_TARGET_SLAVE_BASE_ADDR32h40000000;parameter integer C_M_AXI_BURST_LEN16;parameter integer C_M_AXI_ID_WIDTH1;parameter integer C_M_AXI_ADDR_WIDTH32;parameter integer C_M_AXI_DATA_WIDTH32;parameter integer C_M_AXI_AWUSER_WIDTH0;parameter integer C_M_AXI_ARUSER_WIDTH0;parameter integer C_M_AXI_WUSER_WIDTH0;parameter integer C_M_AXI_RUSER_WIDTH0;parameter integer C_M_AXI_BUSER_WIDTH0;parameter integer C_S_AXI_ID_WIDTH1;parameter integer C_S_AXI_DATA_WIDTH32;parameter integer C_S_AXI_ADDR_WIDTH32;parameter integer C_S_AXI_AWUSER_WIDTH0;parameter integer C_S_AXI_ARUSER_WIDTH0;parameter integer C_S_AXI_WUSER_WIDTH0;parameter integer C_S_AXI_RUSER_WIDTH0;parameter integer C_S_AXI_BUSER_WIDTH0;//reg definereg sys_clk;reg sys_rst_n;reg key_init0;//wire definewire compare_done;wire error_flag;wire[C_M_AXI_ID_WIDTH-1:0]m_axi_awid;wire[C_M_AXI_ADDR_WIDTH-1:0]m_axi_awaddr;wire[7:0]m_axi_awlen;wire[2:0]m_axi_awsize;wire[1:0]m_axi_awburst;wire m_axi_awlock;wire[3:0]m_axi_awcache;wire[2:0]m_axi_awprot;wire[3:0]m_axi_awqos;wire[C_M_AXI_AWUSER_WIDTH-1:0]m_axi_awuser;wire m_axi_awvalid;wire m_axi_awready;wire[C_M_AXI_DATA_WIDTH-1:0]m_axi_wdata;wire[C_M_AXI_DATA_WIDTH/8-1:0]m_axi_wstrb;wire m_axi_wlast;wire[C_M_AXI_WUSER_WIDTH-1:0]m_axi_wuser;wire m_axi_wvalid;wire m_axi_wready;wire[C_M_AXI_ID_WIDTH-1:0]m_axi_bid;wire[1:0]m_axi_bresp;wire[C_M_AXI_BUSER_WIDTH-1:0]m_axi_buser;wire m_axi_bvalid;wire m_axi_bready;wire[C_M_AXI_ID_WIDTH-1:0]m_axi_arid;wire[C_M_AXI_ADDR_WIDTH-1:0]m_axi_araddr;wire[7:0]m_axi_arlen;wire[2:0]m_axi_arsize;wire[1:0]m_axi_arburst;wire m_axi_arlock;wire[3:0]m_axi_arcache;wire[2:0]m_axi_arprot;wire[3:0]m_axi_arqos;wire[C_M_AXI_ARUSER_WIDTH-1:0]m_axi_aruser;wire m_axi_arvalid;wire m_axi_arready;wire[C_M_AXI_ID_WIDTH-1:0]m_axi_rid;wire[C_M_AXI_DATA_WIDTH-1:0]m_axi_rdata;wire[1:0]m_axi_rresp;wire m_axi_rlast;wire[C_M_AXI_RUSER_WIDTH-1:0]m_axi_ruser;wire m_axi_rvalid;wire m_axi_rready;//信号初始化initial begin sys_clk1b0;sys_rst_n1b0;key_init1b0;#200sys_rst_n1b1;#1000key_init1b1;end//产生时钟always #(CLK_PERIOD/2)sys_clk~sys_clk;axi4_rw_test_v1_0_M_AXI #(.C_M_TARGET_SLAVE_BASE_ADDR(C_M_AXI_TARGET_SLAVE_BASE_ADDR),.C_M_AXI_BURST_LEN(C_M_AXI_BURST_LEN),.C_M_AXI_ID_WIDTH(C_M_AXI_ID_WIDTH),.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),.C_M_AXI_DATA_WIDTH(C_M_AXI_DATA_WIDTH),.C_M_AXI_AWUSER_WIDTH(C_M_AXI_AWUSER_WIDTH),.C_M_AXI_ARUSER_WIDTH(C_M_AXI_ARUSER_WIDTH),.C_M_AXI_WUSER_WIDTH(C_M_AXI_WUSER_WIDTH),.C_M_AXI_RUSER_WIDTH(C_M_AXI_RUSER_WIDTH),.C_M_AXI_BUSER_WIDTH(C_M_AXI_BUSER_WIDTH))axi4_rw_test_v1_0_M_AXI_inst(.INIT_AXI_TXN(key_init),.TXN_DONE(compare_done),.ERROR(error_flag),.M_AXI_ACLK(sys_clk),.M_AXI_ARESETN(sys_rst_n),.M_AXI_AWID(m_axi_awid),.M_AXI_AWADDR(m_axi_awaddr),.M_AXI_AWLEN(m_axi_awlen),.M_AXI_AWSIZE(m_axi_awsize),.M_AXI_AWBURST(m_axi_awburst),.M_AXI_AWLOCK(m_axi_awlock),.M_AXI_AWCACHE(m_axi_awcache),.M_AXI_AWPROT(m_axi_awprot),.M_AXI_AWQOS(m_axi_awqos),.M_AXI_AWUSER(m_axi_awuser),.M_AXI_AWVALID(m_axi_awvalid),.M_AXI_AWREADY(m_axi_awready),.M_AXI_WDATA(m_axi_wdata),.M_AXI_WSTRB(m_axi_wstrb),.M_AXI_WLAST(m_axi_wlast),.M_AXI_WUSER(m_axi_wuser),.M_AXI_WVALID(m_axi_wvalid),.M_AXI_WREADY(m_axi_wready),.M_AXI_BID(m_axi_bid),.M_AXI_BRESP(m_axi_bresp),.M_AXI_BUSER(m_axi_buser),.M_AXI_BVALID(m_axi_bvalid),.M_AXI_BREADY(m_axi_bready),.M_AXI_ARID(m_axi_arid),.M_AXI_ARADDR(m_axi_araddr),.M_AXI_ARLEN(m_axi_arlen),.M_AXI_ARSIZE(m_axi_arsize),.M_AXI_ARBURST(m_axi_arburst),.M_AXI_ARLOCK(m_axi_arlock),.M_AXI_ARCACHE(m_axi_arcache),.M_AXI_ARPROT(m_axi_arprot),.M_AXI_ARQOS(m_axi_arqos),.M_AXI_ARUSER(m_axi_aruser),.M_AXI_ARVALID(m_axi_arvalid),.M_AXI_ARREADY(m_axi_arready),.M_AXI_RID(m_axi_rid),.M_AXI_RDATA(m_axi_rdata),.M_AXI_RRESP(m_axi_rresp),.M_AXI_RLAST(m_axi_rlast),.M_AXI_RUSER(m_axi_ruser),.M_AXI_RVALID(m_axi_rvalid),.M_AXI_RREADY(m_axi_rready));axi4_slave_v1_0_S_AXI #(.C_S_AXI_ID_WIDTH(C_S_AXI_ID_WIDTH),.C_S_AXI_DATA_WIDTH(C_S_AXI_DATA_WIDTH),.C_S_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH),.C_S_AXI_AWUSER_WIDTH(C_S_AXI_AWUSER_WIDTH),.C_S_AXI_ARUSER_WIDTH(C_S_AXI_ARUSER_WIDTH),.C_S_AXI_WUSER_WIDTH(C_S_AXI_WUSER_WIDTH),.C_S_AXI_RUSER_WIDTH(C_S_AXI_RUSER_WIDTH),.C_S_AXI_BUSER_WIDTH(C_S_AXI_BUSER_WIDTH))axi4_slave_v1_0_S_AXI_inst(.S_AXI_ACLK(sys_clk),.S_AXI_ARESETN(sys_rst_n),.S_AXI_AWID(m_axi_awid),.S_AXI_AWADDR(m_axi_awaddr),.S_AXI_AWLEN(m_axi_awlen),.S_AXI_AWSIZE(m_axi_awsize),.S_AXI_AWBURST(m_axi_awburst),.S_AXI_AWLOCK(m_axi_awlock),.S_AXI_AWCACHE(m_axi_awcache),.S_AXI_AWPROT(m_axi_awprot),.S_AXI_AWQOS(m_axi_awqos),.S_AXI_AWREGION(m_axi_awregion),.S_AXI_AWUSER(m_axi_awuser),.S_AXI_AWVALID(m_axi_awvalid),.S_AXI_AWREADY(m_axi_awready),.S_AXI_WDATA(m_axi_wdata),.S_AXI_WSTRB(m_axi_wstrb),.S_AXI_WLAST(m_axi_wlast),.S_AXI_WUSER(m_axi_wuser),.S_AXI_WVALID(m_axi_wvalid),.S_AXI_WREADY(m_axi_wready),.S_AXI_BID(m_axi_bid),.S_AXI_BRESP(m_axi_bresp),.S_AXI_BUSER(m_axi_buser),.S_AXI_BVALID(m_axi_bvalid),.S_AXI_BREADY(m_axi_bready),.S_AXI_ARID(m_axi_arid),.S_AXI_ARADDR(m_axi_araddr),.S_AXI_ARLEN(m_axi_arlen),.S_AXI_ARSIZE(m_axi_arsize),.S_AXI_ARBURST(m_axi_arburst),.S_AXI_ARLOCK(m_axi_arlock),.S_AXI_ARCACHE(m_axi_arcache),.S_AXI_ARPROT(m_axi_arprot),.S_AXI_ARQOS(m_axi_arqos),.S_AXI_ARREGION(m_axi_arregion),.S_AXI_ARUSER(m_axi_aruser),.S_AXI_ARVALID(m_axi_arvalid),.S_AXI_ARREADY(m_axi_arready),.S_AXI_RID(m_axi_rid),.S_AXI_RDATA(m_axi_rdata),.S_AXI_RRESP(m_axi_rresp),.S_AXI_RLAST(m_axi_rlast),.S_AXI_RUSER(m_axi_ruser),.S_AXI_RVALID(m_axi_rvalid),.S_AXI_RREADY(m_axi_rready));endmodule5.开始仿真在仿真文件中加入这三个文件记住将tb_axi4_rw_test_v1_0_M_AXI.v设为顶层之后开启仿真在打开的wave窗口删除modelsim自己给的信号并添加axi4_rw_test_v1_0_M_AXI_inst的信号进入wave窗口添加之后修改进制为10进制在命令行中输入run 100us得到以下结果若要将modelsim中的信号分组选中要分组的信号邮件点击group…;若要修改信号颜色右击信号选择Properties…在波形窗口ctrls可以保存wave.do将界面及设置保存下来之后在波形界面点击fileLoad…选中保存的wave.do可以将波形界面复现6.搭建bd文件在工程中加入key_debounce右击选择block design界面选择add module再加入axi4_rw_testIP核修改基地址再加入Utility Vector Logic核,改逻辑为not并设置位宽为1连接如图信号之后点击自动连接若要更换互联模块为AXI SmartConnect可以先删除AXI Interconnect然后添加AXI SmartConnectAXI SmartConnect的设置如下并连线接下来将key引出端口并改名以及这两个端口创建pin.xdc:#----------------------PL_KEY---------------------------set_property-dict{PACKAGE_PIN L14 IOSTANDARD LVCMOS33}[get_ports key_init]#----------------------PL_LED---------------------------#底板 set_property-dict{PACKAGE_PIN H15 IOSTANDARD LVCMOS33}[get_ports compare_done]set_property-dict{PACKAGE_PIN L15 IOSTANDARD LVCMOS33}[get_ports error_flag]之后老流程生成xsa文件。7.创建vitis工程并编写代码老步骤创建工程并新建main.c:#includestdio.h#includexil_printf.h#includexil_io.h#includexil_cache.h#defineRW_DDR_BASE_ADDRESS0x10000000intmain(){charc;intdata;printf(AXI4 PL write and read PS DDR test \r\n);// Xil_DCacheDisable();while(1){scanf(%c,c);if(cc){Xil_DCacheInvalidateRange(RW_DDR_BASE_ADDRESS,4096);printf(PS start read DDR);for(inti0;i4096;ii4){dataXil_In32(RW_DDR_BASE_ADDRESSi);printf(Address is %d, Data is %d.\r\n,i,data);}}}}总结工程分享pl_rw_ddr.zip